FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
OPT_RXDIS
OPT_RXINV
2008[5]
2008[4]
0
0
0
0
R/W
R/W
Configures OPT_RX to an analog input to the optical UART comparator or as a digital
input/output, DIO1.
0 = OPT_RX, 1 = DIO1.
Inverts the result from the OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
OPT_TXE[1:0]
2007[7:6]
00
00
R/W
OPT_TXE [1:0]
00
01
10
Function
OPT_TX
DIO2
WPULSE
11
RPULSE
OPT_TXINV
OPT_TXMOD
PLL_OK
PLS_MAXWIDTH
[7:0]
PLS_INTERVAL
[7:0]
PLS_INV
PREBOOT
PREG[16:0]
2008[0]
2008[1]
2003[6]
2080[7:0]
2081[7:0]
2004[6]
SFRB2[7]
201C[2:0]
201D[7:0]
201E[7:2]
0
0
0
FF
0
0
4
0
0
0
0
0
FF
0
0
NV
NV
NV
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Inverts OPT_TX when 1. This inversion occurs before modulation.
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated
when it would otherwise have been zero. The modulation is applied after any inversion
caused by OPT_TXINV .
Indicates that system power is present and the clock generation PLL is settled.
Determines the maximum width of the pulse (low going pulse).
The maximum pulse width is (2*PLS_MAXWIDTH + 1)*T I . Where T I is PLS_INTERVAL .
If PLS_INTERVAL = 0, T I is the sample time (397 μs). If set to 255, pulse width control
is disabled and pulses are output with a 50% duty cycle.
For PULSE_W and PULSE_V only, if the FIFO is used, PLS_INTERVAL must be set to
81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the
CE issues them.
Inverts the polarity of the pulse outputs Normally, these pulses are active low. When
inverted, they become active high.
Indicates that the preboot sequence is active.
RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.
0x0FFBF ≤ PREG ≤ 0x10040
PREG [16:0] and QREG [1:0] are separate in hardware but can be programmed with a
single number calculated by the MPU. . PREG [16:0] and QREG [1:0] are non-volatile,
but have no correcting function in SLEEP mode.
The duration of the pre-summer, in samples.
PRE_SAMPS[1:0] 2001[7:6]
0
0
R/W
PRE_SAMPS [1:0]
00
01
10
11
Pre-Summer Duration
42
50
84
100
Rev 2
91
相关PDF资料
71M6541F-DB DEMO BOARD 71M6541F
71M6543F-DB-CT DEMO BOARD 71M6543F-DB-CT
72-CNV-5 CONVERTER RS-232 TO RS-422 5V
72346-001 72346-1-SCA-II REC
72347-001LF CONN RECEPT SCA2 20POS VERT PCB
72436-001LF 80POS EXT HT. REC SCA-2
72442-201LF CONN RECEPT SCA2 80POS VERT PCB
72512-001 5 X 12 COVERS
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